201 search results - page 3 / 41 » Reducing Test Application Time Through Test Data Mutation En... |
VTS
1997
IEEE
13 years 11 months ago
1997
IEEE
Accumulators based on addition or subtraction can be used as test pattern generators. Some circuits, however, require long test lengths if the parameters of the accumulator are no...
ITC
2002
IEEE
14 years 13 days ago
2002
IEEE
Significant reductions in test application times can be achieved through parallelizing core tests; however, simultaneous test of various cores may result in exceeding power thres...
DFT
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
DATE
1999
IEEE
13 years 12 months ago
1999
IEEE
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
Scan compression has emerged as the most successful solution to solve the problem of rising manufacturing test cost. Compression technology is not hierarchical in nature. Hierarch...