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ET
2010
113views more  ET 2010»
13 years 4 months ago
Calibration and Test Time Reduction Techniques for Digitally-Calibrated Designs: an ADC Case Study
Modern mixed-signal/RF circuits with a digital calibration capability could achieve significant performance improvement through calibration. However, the calibration process often ...
Hsiu-Ming Chang, Kuan-Yu Lin, Kwang-Ting (Tim) Che...
ICASSP
2011
IEEE
12 years 11 months ago
Enhanced coding of high-frequency tonal components in MPEG-D USAC through joint application of ESBR and sinusoidal modeling
The new eSBR tool of MPEG-D Universal Speech and Audio Coding offers a great advantage in compression of high frequency content, however it produces audible artifacts for sounds w...
Tomasz Zernicki, Maciej Bartkowiak, Marek Domanski
CCGRID
2007
IEEE
14 years 1 months ago
Build-and-Test Workloads for Grid Middleware: Problem, Analysis, and Applications
The Grid promise is starting to materialize today: largescale multi-site infrastructures have grown to assist the work of scientists from all around the world. This tremendous gro...
Alexandru Iosup, Dick H. J. Epema
DATE
2007
IEEE
81views Hardware» more  DATE 2007»
14 years 1 months ago
Using the inter- and intra-switch regularity in NoC switch testing
This paper proposes an efficient test methodology to test switches in a Network-on-Chip (NoC) architecture. A switch in an NoC consists of a number of ports and a router. Using th...
Mohammad Hosseinabady, Atefe Dalirsani, Zainalabed...
CASES
2003
ACM
14 years 24 days ago
Power efficient encoding techniques for off-chip data buses
Reducing the power consumption of computing devices has gained a lot of attention recently. Many research works have focused on reducing power consumption in the off-chip buses as...
Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Wa...