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» Reducing cache misses through programmable decoders
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170
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MICRO
1997
IEEE
90views Hardware» more  MICRO 1997»
15 years 11 months ago
ProfileMe: Hardware Support for Instruction-Level Profiling on Out-of-Order Processors
Profile data is valuable for identifying performance bottlenecks and guiding optimizations. Periodic sampling of a processor's performance monitoring hardware is an effective...
Jeffrey Dean, James E. Hicks, Carl A. Waldspurger,...
MICRO
2007
IEEE
184views Hardware» more  MICRO 2007»
16 years 1 months ago
Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures
The recent design shift towards multicore processors has spawned a significant amount of research in the area of program parallelization. The future abundance of cores on a singl...
Michael L. Chu, Rajiv A. Ravindran, Scott A. Mahlk...
CF
2005
ACM
15 years 9 months ago
A case for a working-set-based memory hierarchy
Modern microprocessor designs continue to obtain impressive performance gains through increasing clock rates and advances in the parallelism obtained via micro-architecture design...
Steve Carr, Soner Önder
187
Voted
DATE
2003
IEEE
141views Hardware» more  DATE 2003»
16 years 20 days ago
On-chip Stack Based Memory Organization for Low Power Embedded Architectures
This paper presents a on-chip stack based memory organization that effectively reduces the energy dissipation in programmable embedded system architectures. Most embedded systems ...
Mahesh Mamidipaka, Nikil D. Dutt
178
Voted
EUROCRYPT
2010
Springer
16 years 5 days ago
Protecting Circuits from Leakage: the Computationally-Bounded and Noisy Cases
Abstract. Physical computational devices leak side-channel information that may, and often does, reveal secret internal states. We present a general transformation that compiles an...
Sebastian Faust, Tal Rabin, Leonid Reyzin, Eran Tr...