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IWSOC
2003
IEEE
97views Hardware» more  IWSOC 2003»
14 years 26 days ago
Evaluating Template-Based Instruction Compression on Transport Triggered Architectures
In embedded systems, memory is one of the most expensive resources. Due to this, program code size has turned out to be one of the most critical design constraints. Code compressi...
Jari Heikkinen, Tommi Rantanen, Andrea G. M. Cilio...
DATE
2008
IEEE
139views Hardware» more  DATE 2008»
14 years 2 months ago
Instruction Re-encoding Facilitating Dense Embedded Code
Reducing the code size of embedded applications is one of the important constraint in embedded system design. Code compression can provide substantial savings in terms of size. In...
Talal Bonny, Jörg Henkel
ISSS
1996
IEEE
125views Hardware» more  ISSS 1996»
13 years 11 months ago
Size-Constrained Code Placement for Cache Miss Rate Reduction
In design of an embedded system with a cache, it is important to minimize the cache miss rate to reduce the power consumption as well as to improvethe performance of the system. W...
Hiroyuki Tomiyama, Hiroto Yasuura
EUC
2005
Springer
14 years 1 months ago
Optimizing Nested Loops with Iterational and Instructional Retiming
Abstract. Embedded systems have strict timing and code size requirements. Retiming is one of the most important optimization techniques to improve the execution time of loops by in...
Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edw...
LCTRTS
2007
Springer
14 years 1 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...