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» Reducing computational complexity with array predicates
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TCAD
2008
112views more  TCAD 2008»
13 years 7 months ago
Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs
Boolean matching is one of the enabling techniques for technology mapping and logic resynthesis of Field Programmable Gate Array (FPGA). SAT-based Boolean matching (SAT-BM) has bee...
Yu Hu, Victor Shih, Rupak Majumdar, Lei He
JUCS
2000
135views more  JUCS 2000»
13 years 7 months ago
The Price of Routing in FPGAs
: Studying the architectural evolution of mainstream field programmable gate arrays (FPGAs) leads to the following remark: in these circuits, the proportion of silicon devoted to r...
Florent de Dinechin
BMCBI
2007
133views more  BMCBI 2007»
13 years 8 months ago
An efficient pseudomedian filter for tiling microrrays
Background: Tiling microarrays are becoming an essential technology in the functional genomics toolbox. They have been applied to the tasks of novel transcript identification, elu...
Thomas E. Royce, Nicholas Carriero, Mark B. Gerste...
MICRO
2000
IEEE
176views Hardware» more  MICRO 2000»
13 years 7 months ago
An Advanced Optimizer for the IA-64 Architecture
level of abstraction, compared with the program representation for scalar optimizations. For example, loop unrolling and loop unrolland-jam transformations exploit the large regist...
Rakesh Krishnaiyer, Dattatraya Kulkarni, Daniel M....
FCCM
2008
IEEE
212views VLSI» more  FCCM 2008»
14 years 2 months ago
Map-reduce as a Programming Model for Custom Computing Machines
The map-reduce model requires users to express their problem in terms of a map function that processes single records in a stream, and a reduce function that merges all mapped out...
Jackson H. C. Yeung, C. C. Tsang, Kuen Hung Tsoi, ...