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» Reducing the Costs of Bounded-Exhaustive Testing
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ICCAD
2009
IEEE
94views Hardware» more  ICCAD 2009»
13 years 5 months ago
Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint
We propose a layout-driven test-architecture design and optimization technique for core-based system-on-chips (SoCs) that are fabricated using three-dimensional (3D) integration. ...
Li Jiang, Qiang Xu, Krishnendu Chakrabarty, T. M. ...
SIGSOFT
2010
ACM
13 years 5 months ago
Rethinking the economics of software engineering
Reliance on skilled developers reduces the return on investment for important software engineering tasks such as establishing program correctness. This position paper introduces a...
Todd W. Schiller, Michael D. Ernst
DATE
2005
IEEE
107views Hardware» more  DATE 2005»
14 years 1 months ago
Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores
Many SOCs today contain both digital and analog embedded cores. Even though the test cost for such mixed-signal SOCs is significantly higher than that for digital SOCs, most prio...
Anuja Sehgal, Fang Liu, Sule Ozev, Krishnendu Chak...
ATS
2001
IEEE
172views Hardware» more  ATS 2001»
13 years 11 months ago
A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters
Testing and diagnosis are important issues in system-onchip (SOC) development, as more and more embedded cores are being integrated into the chips. In this paper we propose a buil...
Chih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih...
ICFEM
2003
Springer
14 years 24 days ago
Formalization, Testing and Execution of a Use Case Diagram
Abstract. Errors in a requirements model have prolonged detrimental effects on reliability, cost, and safety of a software system. It is very costly to fix these errors in later ...
Wuwei Shen, Shaoying Liu