221 search results - page 11 / 45 » Reducing the Interconnection Network Cost of Chip Multiproce... |
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
— Recent efforts to address microprocessor power dissipation through aggressive supply voltage scaling and power management require that designers be increasingly cognizant of po...
ERSA
2006
13 years 9 months ago
2006
Abstract-- With the constantly increasing gate capacity of FPGAs, a single FPGA chip is able to employ large-scale applications. To connect a large number of computational nodes, N...
ISCAS
2008
IEEE
14 years 2 months ago
2008
IEEE
Abstract— As the number of processing cores that are integrated into a chip multiprocessors (CMP) continues to grow, the network-on-chip paradigm has emerged as a promising solut...
ASPDAC
2009
ACM
14 years 8 days ago
2009
ACM
– The phenomenon of digital convergence and increasing application complexity today is motivating the design of chip multiprocessor (CMP) applications with multiple use cases. Mo...
CONEXT
2010
ACM
13 years 5 months ago
2010
ACM
Fundamental limitations of traditional data center network architectures have led to the development of architectures that provide enormous bisection bandwidth for up to hundreds ...