Sciweavers

221 search results - page 27 / 45
» Reducing the Interconnection Network Cost of Chip Multiproce...
Sort
View
GLVLSI
2005
IEEE
104views VLSI» more  GLVLSI 2005»
14 years 1 months ago
Wave-pipelined 2-slot time division multiplexed (WP/2-TDM) routing
The ever-increasing number of transistors on a chip has resulted in very large scale integration (VLSI) systems whose performance and manufacturing costs are driven by on-chip wir...
Ajay Joshi, Jeffrey A. Davis
RTSS
2008
IEEE
14 years 1 months ago
Priority Assignment for Real-Time Wormhole Communication in On-Chip Networks
—Wormhole switching with fixed priority preemption has been proposed as a possible solution for real-time on-chip communication. However, none of current priority assignment pol...
Zheng Shi, Alan Burns
TGC
2010
Springer
13 years 5 months ago
CarPal: Interconnecting Overlay Networks for a Community-Driven Shared Mobility
Car sharing and car pooling have proven to be an effective solution to reduce the amount of running vehicles by increasing the number of passengers per car amongst medium/big commu...
Vincenzo Dezani-Ciancaglini, Luigi Liquori, Lauren...
DATE
2005
IEEE
165views Hardware» more  DATE 2005»
14 years 1 months ago
Flexible Hardware/Software Support for Message Passing on a Distributed Shared Memory Architecture
With the advent of multi-processor systems on a chip, the interest for message passing libraries has revived. Message passing helps in mastering the design complexity of parallel ...
Francesco Poletti, Antonio Poggiali, Paul Marchal
DATE
2008
IEEE
77views Hardware» more  DATE 2008»
14 years 2 months ago
Re-Examining the Use of Network-on-Chip as Test Access Mechanism
Existing work on testing NoC-based systems advocates to reuse the on-chip network itself as test access mechanism (TAM) to transport test data to/from embedded cores. While this m...
Feng Yuan, Lin Huang, Qiang Xu