221 search results - page 34 / 45 » Reducing the Interconnection Network Cost of Chip Multiproce... |
CHES
2005
Springer
2005
Springer
Scalable Hardware for Sparse Systems of Linear Equations, with Applications to Integer Factorization
14 years 1 months ago
Motivated by the goal of factoring large integers using the Number Field Sieve, several special-purpose hardware designs have been recently proposed for solving large sparse system...
DSD
2002
IEEE
14 years 13 days ago
2002
IEEE
Continuing VLSI technology scaling raises several deep submicron (DSM) problems like relatively slow interconnect, power dissipation and distribution, and signal integrity. Those ...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
—Dynamic Thermal Management techniques have been widely accepted as a thermal solution for their low cost and simplicity. The techniques have been used to manage the heat dissipa...
MICRO
2009
IEEE
14 years 2 months ago
2009
IEEE
As technology scaling drives the number of processor cores upward, current on-chip routers consume substantial portions of chip area and power budgets. Since existing research has...
SPAA
2000
ACM
13 years 11 months ago
2000
ACM
Modern VLSI processing supports a two-dimensional surface for active devices along with multiple stacked layers of interconnect. With the advent of planarization, the number of la...