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ICCAD
2003
IEEE
152views Hardware» more  ICCAD 2003»
14 years 7 months ago
Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches
On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In deep sub-micron technology, the subthreshold leakage power is becoming...
Nam Sung Kim, David Blaauw, Trevor N. Mudge
ASIACRYPT
2009
Springer
14 years 5 months ago
Improved Generic Algorithms for 3-Collisions
An r-collision for a function is a set of r distinct inputs with identical outputs. Actually finding r-collisions for a random map over a finite set of cardinality N requires at ...
Antoine Joux, Stefan Lucks
TVLSI
2002
100views more  TVLSI 2002»
13 years 10 months ago
Architectural strategies for low-power VLSI turbo decoders
Abstract--The use of "turbo codes" has been proposed for several applications, including the development of wireless systems, where highly reliable transmission is requir...
Guido Masera, M. Mazza, Gianluca Piccinini, F. Vig...
EGH
2004
Springer
14 years 4 months ago
A programmable vertex shader with fixed-point SIMD datapath for low power wireless applications
The real time 3D graphics becomes one of the attractive applications for 3G wireless terminals although their battery lifetime and memory bandwidth limit the system resources for ...
Ju-Ho Sohn, Ramchan Woo, Hoi-Jun Yoo
DAC
2000
ACM
14 years 12 months ago
Code compression for low power embedded system design
erse approaches at all levels of abstraction starting from the physical level up to the system level. Experience shows that a highlevel method may have a larger impact since the de...
Haris Lekatsas, Jörg Henkel, Wayne Wolf