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» Reducing the complexity of the issue logic
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ISLPED
2005
ACM
110views Hardware» more  ISLPED 2005»
14 years 1 months ago
Complexity reduction in an nRERL microprocessor
We describe an adiabatic microprocessor implemented with a reversible logic, nRERL [1]. We employed an 8-phase clocked power instead of 6-phase one to reduce the number of buffers...
Seokkee Kim, Soo-Ik Chae
CAMP
2005
IEEE
14 years 1 months ago
Bio-Inspired Computing Architectures: The Embryonics Approach
Abstract— The promise of next-generation computer technologies, such as nano-electronics, implies a number of serious alterations to the design flow of digital circuits. One of ...
Gianluca Tempesti, Daniel Mange, André Stau...
ISLPED
2003
ACM
88views Hardware» more  ISLPED 2003»
14 years 23 days ago
Reducing data cache energy consumption via cached load/store queue
High-performance processors use a large set–associative L1 data cache with multiple ports. As clock speeds and size increase such a cache consumes a significant percentage of t...
Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru...
ECSQARU
2009
Springer
14 years 2 months ago
An Algorithm for Generating Arguments in Classical Predicate Logic
Abstract. There are a number of frameworks for modelling argumentation in logic. They incorporate a formal representation of individual arguments and techniques for comparing con...
Vasiliki Efstathiou, Anthony Hunter
DSD
2003
IEEE
121views Hardware» more  DSD 2003»
14 years 24 days ago
CCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip Multiprocessors
With shrinking feature size of silicon fabrication technology, architects are putting more and more logic into a single die. While one might opt to use these transistors for build...
Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemi...