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» Reducing the number of clock variables of timed automata
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CIKM
2007
Springer
14 years 1 months ago
Sigma encoded inverted files
Compression of term frequency lists and very long document-id lists within an inverted file search engine are examined. Several compression schemes are compared including Elias γ...
Andrew Trotman, Vikram Subramanya
DATE
2010
IEEE
126views Hardware» more  DATE 2010»
13 years 11 months ago
Scenario-based analysis and synthesis of real-time systems using uppaal
Abstract. We propose an approach to scenario-based analysis and synthesis of real-time embedded systems. The inter-process behaviors of a system are modeled as a set of driving uni...
Kim Guldstrand Larsen, Shuhao Li, Brian Nielsen, S...
ISQED
2007
IEEE
162views Hardware» more  ISQED 2007»
14 years 1 months ago
Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...
David Zaretsky, Gaurav Mittal, Robert P. Dick, Pri...
RTCSA
1999
IEEE
13 years 12 months ago
A Symbolic Model Checker for Testing ASTRAL Real-Time Specifications
ASTRAL is a high-level formal specification language for real-time (infinite state) systems. It is provided with structuring mechanisms that allow one to build modularized specifi...
Zhe Dang, Richard A. Kemmerer
ICRA
2003
IEEE
95views Robotics» more  ICRA 2003»
14 years 27 days ago
Bilateral time-scaling for control of task freedoms of a constrained nonholonomic system
— We explore the control of a nonholonomic robot subject to additional constraints on the state variables. In our problem, the user specifies the path of a subset of the state v...
Siddhartha S. Srinivasa, Michael Erdmann, Matthew ...