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» Reducing traffic generated by conflict misses in caches
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HPCA
2000
IEEE
13 years 12 months ago
Modified LRU Policies for Improving Second-Level Cache Behavior
Main memory accesses continue to be a significant bottleneck for applications whose working sets do not fit in second-level caches. With the trend of greater associativity in seco...
Wayne A. Wong, Jean-Loup Baer
HPCC
2009
Springer
14 years 2 days ago
On Instruction-Level Method for Reducing Cache Penalties in Embedded VLIW Processors
Usual cache optimisation techniques for high performance computing are difficult to apply in embedded VLIW applications. First, embedded applications are not always well structur...
Samir Ammenouche, Sid Ahmed Ali Touati, William Ja...
ISCA
1996
IEEE
120views Hardware» more  ISCA 1996»
13 years 11 months ago
Missing the Memory Wall: The Case for Processor/Memory Integration
Current high performance computer systems use complex, large superscalar CPUs that interface to the main memory through a hierarchy of caches and interconnect systems. These CPU-c...
Ashley Saulsbury, Fong Pong, Andreas Nowatzyk
TON
2008
88views more  TON 2008»
13 years 7 months ago
Traffic modeling and proportional partial caching for peer-to-peer systems
Peer-to-peer (P2P) file sharing systems generate a major portion of the Internet traffic, and this portion is expected to increase in the future. We explore the potential of deploy...
Mohamed Hefeeda, Osama Saleh
ISCA
2010
IEEE
232views Hardware» more  ISCA 2010»
14 years 16 days ago
Data marshaling for multi-core architectures
Previous research has shown that Staged Execution (SE), i.e., dividing a program into segments and executing each segment at the core that has the data and/or functionality to bes...
M. Aater Suleman, Onur Mutlu, José A. Joao,...