49 search results - page 5 / 10 » Reduction of Power Dissipation during Scan Testing by Test V... |
ICCAD
2007
IEEE
14 years 4 months ago
2007
IEEE
— This paper proposes a selective pattern-compression scheme to minimize both test power and test data volume during scan-based testing. The proposed scheme will selectively supp...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can...
ITC
2003
IEEE
14 years 24 days ago
2003
IEEE
As semiconductor manufacturing technology advances, power dissipation and noise in scan testing has become a critical problem. In our studies on practical LSI manufacturing, we ha...
ITC
1998
IEEE
13 years 11 months ago
1998
IEEE
This work proposes an approach to generate weighted random patterns which can maximally excite a circuit during its burn-in testing. The approach is based on a probability model a...
DFT
1999
IEEE
13 years 12 months ago
1999
IEEE
In the last decade, researchers have devoted increasing efforts to reduce the average power consumption in VLSI systems during normal operation mode, while power consumption durin...