73 search results - page 7 / 15 » Reduction of interpolants for logic synthesis |
TCAD
2008
13 years 7 months ago
2008
The relatively poor scaling of interconnect in modern digital circuits necessitates a number of design optimizations, which must typically be iterated several times to meet the spe...
ISLPED
1995
ACM
13 years 11 months ago
1995
ACM
We present a technique that automatically synthesizes nite state machines with gated clocks to reduce the power dissipation of the nal implementation. We describe a new transfor...
ITC
1999
IEEE
13 years 12 months ago
1999
IEEE
A new synthesis technique for designing finite state machines with on-line parity checking is presented. The output logic and the next-state logic of the finite state machines are...
FPL
1999
Springer
13 years 12 months ago
1999
Springer
This paper details the development, implementation, and results of Synthia, a system for the synthesis of Finite State Machines (FSMs) to field-programmable logic. Our approach us...
ISVC
2005
Springer
14 years 1 months ago
2005
Springer
Abstract. We present an appearance-based 3D hand posture estimation method that determines a ranked set of possible hand posture candidates from an unmarked hand image, based on an...