39 search results - page 4 / 8 » Register File Architecture Optimization in a Coarse-Grained ... |
IEEEPACT
2002
IEEE
13 years 12 months ago
2002
IEEE
In this paper, we describe an algorithm and implementation of locality optimizations for architectures with instruction sets such as Intel’s SSE and Motorola’s AltiVec that su...
EUROPAR
2009
Springer
13 years 10 months ago
2009
Springer
Abstract. We present a hardware mechanism which dynamically detects uniform and affine vectors used in Graphics Processing Units, to minimize pressure on the register file and redu...
PACS
2004
Springer
14 years 9 days ago
2004
Springer
In recent years, processor manufacturers have converged on two types of register file architectures. Both IBM with its POWER series and Intel with its Pentium series are using a ...
VLSISP
2008
13 years 6 months ago
2008
The compiler is generally regarded as the most important software component that supports a processor design to achieve success. This paper describes our application of the open re...
ISCA
2003
IEEE
14 years 7 days ago
2003
IEEE
Current-generation microprocessors are designed to process instructions with one and two source operands at equal cost. Handling two source operands requires multiple ports for ea...