32 search results - page 3 / 7 » Register File Design Considerations in Dynamically Scheduled... |
HPCA
1998
IEEE
13 years 11 months ago
1998
IEEE
A novel dynamic register renaming approach is proposed in this work. The key idea of the novel scheme is to delay the allocation of physical registers until a late stage in the pi...
ISCA
2003
IEEE
14 years 7 days ago
2003
IEEE
Current-generation microprocessors are designed to process instructions with one and two source operands at equal cost. Handling two source operands requires multiple ports for ea...
ISCA
2011
IEEE
12 years 10 months ago
2011
IEEE
Conventional high-performance processors utilize register renaming and complex broadcast-based scheduling logic to steer instructions into a small number of heavily-pipelined exec...
DATE
2004
IEEE
13 years 10 months ago
2004
IEEE
Many high-end DSP processors employ both multiple memory banks and heterogeneous register files to improve performance and power consumption. The complexity of such architectures ...
HPCA
1997
IEEE
13 years 11 months ago
1997
IEEE
This paper represents a design study of the datapath for a very long instruction word (VLIW) video signal processor (VSP). VLIW architectures provide high parallelism and excellen...