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VLSID
2004
IEEE
107views VLSI» more  VLSID 2004»
14 years 8 months ago
Performance Analysis of Inter Cluster Communication Methods in VLIW Architecture
With increasing demands for high performance by embedded systems, especially by digital signal processing applications, embedded processors must increase available instruction lev...
Sourabh Saluja, Anshul Kumar
VLSID
2001
IEEE
129views VLSI» more  VLSID 2001»
14 years 8 months ago
Design Of Provably Correct Storage Arrays
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann
FMCAD
2009
Springer
14 years 2 months ago
Retiming and resynthesis with sweep are complete for sequential transformation
— There is a long history of investigations and debates on whether a sequence of retiming and resynthesis is complete for all sequential transformations (on steady states). It ha...
Hai Zhou
ASAP
2008
IEEE
118views Hardware» more  ASAP 2008»
14 years 2 months ago
Bit matrix multiplication in commodity processors
Registers in processors generally contain words or, with the addition of multimedia extensions, short vectors of subwords of bytes or 16-bit elements. In this paper, we view the c...
Yedidya Hilewitz, Cédric Lauradoux, Ruby B....
ISORC
2008
IEEE
14 years 2 months ago
Hardware Objects for Java
Java, as a safe and platform independent language, avoids access to low-level I/O devices or direct memory access. In standard Java, low-level I/O it not a concern; it is handled ...
Martin Schoeberl, Christian Thalinger, Stephan Kor...