76 search results - page 8 / 16 » Register placement for low power clock network |
DAC
1996
ACM
13 years 11 months ago
1996
ACM
: We presentdesign-for-low-power techniques based on glitch reduction for register-transfer level circuits. We analyze the generation and propagation of glitches in both the contro...
MICRO
2003
IEEE
14 years 27 days ago
2003
IEEE
Energy-efficient processor design is becoming more and more important with technology scaling and with high performance requirements. Supply-voltage scaling is an efficient way to...
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract—Design guidelines for resonant H-tree clock distribution networks are presented in this paper. A distributed model of a two-level resonant H-tree structure is described,...
DAC
2009
ACM
13 years 11 months ago
2009
ACM
Structured ASICs have recently emerged as an exciting alternative to ASIC or FPGA design style as they provide a new trade-off between the high performance of ASIC design and low ...
HOTI
2005
IEEE
14 years 1 months ago
2005
IEEE
A partitioned TCAM-based search engine is presented that increases packet forwarding rate multiple times over traditional TCAMs. The model works for IPv4 and IPv6 packet forwardin...