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» Relaxed memory models: an operational approach
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ASPDAC
2011
ACM
217views Hardware» more  ASPDAC 2011»
12 years 11 months ago
Realization and performance comparison of sequential and weak memory consistency models in network-on-chip based multi-core syst
This paper studies realization and performance comparison of the sequential and weak consistency models in the network-on-chip (NoC) based distributed shared memory (DSM) multi-cor...
Abdul Naeem, Xiaowen Chen, Zhonghai Lu, Axel Jants...
SBMF
2009
Springer
184views Formal Methods» more  SBMF 2009»
14 years 2 months ago
Concolic Testing of the Multi-sector Read Operation for Flash Memory File System
In today’s information society, flash memory has become a virtually indispensable component, particularly for mobile devices. In order for mobile devices to operate successfully...
Moonzoo Kim, Yunho Kim
ISCA
2006
IEEE
144views Hardware» more  ISCA 2006»
13 years 7 months ago
Conditional Memory Ordering
Conventional relaxed memory ordering techniques follow a proactive model: at a synchronization point, a processor makes its own updates to memory available to other processors by ...
Christoph von Praun, Harold W. Cain, Jong-Deok Cho...
ENC
2004
IEEE
13 years 11 months ago
Graph-Based Point Relaxation for 3D Stippling
Point hierarchies are suitable for creating framecoherent animations of 3D models in non-photorealistic styles such as stippling, painterly and other artistic rendering. In this p...
Oscar Meruvia Pastor, Thomas Strotthote
HICSS
2009
IEEE
106views Biometrics» more  HICSS 2009»
14 years 2 months ago
A Radical Approach to Network-on-Chip Operating Systems
Operating systems were created to provide multiple tasks with access to scarce hardware resources like CPU, memory, or storage. Modern programmable hardware, however, may contain ...
Michael Engel, Olaf Spinczyk