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ISQED
2006
IEEE
90views Hardware» more  ISQED 2006»
14 years 1 months ago
Transaction Level Error Susceptibility Model for Bus Based SoC Architectures
System on Chip architectures have traditionally relied upon bus based interconnect for their communication needs. However, increasing bus frequencies and the load on the bus calls...
Ing-Chao Lin, Suresh Srinivasan, Narayanan Vijaykr...
SENSYS
2004
ACM
14 years 28 days ago
An analysis of a large scale habitat monitoring application
Habitat and environmental monitoring is a driving application for wireless sensor networks. We present an analysis of data from a second generation sensor networks deployed during...
Robert Szewczyk, Alan M. Mainwaring, Joseph Polast...
DATE
2009
IEEE
189views Hardware» more  DATE 2009»
14 years 2 months ago
CUFFS: An instruction count based architectural framework for security of MPSoCs
—Multiprocessor System on Chip (MPSoC) architecture is rapidly gaining momentum for modern embedded devices. The vulnerabilities in software on MPSoCs are often exploited to caus...
Krutartha Patel, Sri Parameswaran, Roshan G. Ragel
SBCCI
2005
ACM
123views VLSI» more  SBCCI 2005»
14 years 1 months ago
Fault tolerance overhead in network-on-chip flow control schemes
Flow control mechanisms in Network-on-Chip (NoC) architectures are critical for fast packet propagation across the network and for low idling of network resources. Buffer manageme...
Antonio Pullini, Federico Angiolini, Davide Bertoz...
CCS
2009
ACM
14 years 2 months ago
Can they hear me now?: a security analysis of law enforcement wiretaps
Although modern communications services are susceptible to third-party eavesdropping via a wide range of possible techniques, law enforcement agencies in the US and other countrie...
Micah Sherr, Gaurav Shah, Eric Cronin, Sandy Clark...