282 search results - page 46 / 57 » Reliability- and process-variation aware design of integrate... |
SLIP
2009
ACM
14 years 3 months ago
2009
ACM
Different interconnection structures have been proposed to solve the performance limitation caused by scaling of on-chip global wires. In this paper, we give an overview of curre...
DAC
2011
ACM
12 years 8 months ago
2011
ACM
Clock tree synthesis is one of the most important and challenging problems in 3D ICs. The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with...
ICCAD
2006
IEEE
14 years 5 months ago
2006
IEEE
In this paper, we propose the first wire density driven global routing that considers CMP variation and timing. To enable CMP awareness during global routing, we propose a compac...
DAC
2003
ACM
14 years 10 months ago
2003
ACM
Recent advances in tester technology have led to automatic test equipment (ATE) that can operate at up to several hundred MHz. However, system-on-chip (SOC) scan chains typically ...
FPL
2005
Springer
14 years 2 months ago
2005
Springer
In many industrial processes, an incorrect operation can lead to irreparable damage to people, equipment, or the environment. In order to reduce risks, the electronic control syst...