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ASPDAC
2008
ACM
101views Hardware» more  ASPDAC 2008»
13 years 11 months ago
Interconnect modeling for improved system-level design optimization
Accurate modeling of delay, power, and area of interconnections early in the design phase is crucial for effective system-level optimization. Models presently used in system-level...
Luca P. Carloni, Andrew B. Kahng, Swamy Muddu, Ale...
ISPD
2010
ACM
163views Hardware» more  ISPD 2010»
14 years 3 months ago
A statistical framework for designing on-chip thermal sensing infrastructure in nano-scale systems
Thermal/power issues have become increasingly important with more and more transistors being put on a single chip. Many dynamic thermal/power management techniques have been propo...
Yufu Zhang, Bing Shi, Ankur Srivastava
ISPD
2003
ACM
151views Hardware» more  ISPD 2003»
14 years 2 months ago
Capturing crosstalk-induced waveform for accurate static timing analysis
We propose a method to capture crosstalk-induced noisy waveform for crosstalk-aware static timing analysis. The effects of capacitive coupling noise on timing are conventionally m...
Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera
ICCD
2008
IEEE
202views Hardware» more  ICCD 2008»
14 years 6 months ago
CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework
— Extreme scaling practices in silicon technology are quickly leading to integrated circuit components with limited reliability, where phenomena such as early-transistor failures...
Andrea Pellegrini, Kypros Constantinides, Dan Zhan...
DAC
2006
ACM
14 years 2 months ago
The zen of nonvolatile memories
Silicon technology based nonvolatile memories (NVM) have achieved widespread adoption for code and data storage applications. In the last 30 years, the traditional floating gate ...
Erwin J. Prinz