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» Reliable Systolic Computing Through Redundancy
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ISQED
2005
IEEE
76views Hardware» more  ISQED 2005»
14 years 18 days ago
Technology Mapping for Reliability Enhancement in Logic Synthesis
Abstract— Reliability enhancements are traditionally implemented through redundancies at the system level or through the use of harden-cell-designs at the circuit level. Reliabil...
Zhaojun Wo, Israel Koren
MOBIHOC
2009
ACM
14 years 7 months ago
A practical joint network-channel coding scheme for reliable communication in wireless networks
In this paper, we propose a practical scheme, called Non-Binary Joint Network-Channel Decoding (NB-JNCD) for reliable communication in wireless networks. It seamlessly couples cha...
Zheng Guo, Jie Huang, Bing Wang, Jun-Hong Cui, She...
DAC
2009
ACM
14 years 8 months ago
Improving testability and soft-error resilience through retiming
State elements are increasingly vulnerable to soft errors due to their decreasing size, and the fact that latched errors cannot be completely eliminated by electrical or timing ma...
Smita Krishnaswamy, Igor L. Markov, John P. Hayes
DSN
2008
IEEE
14 years 1 months ago
Enhancing data availability in disk drives through background activities
Latent sector errors in disk drives affect only a few data sectors. They occur silently and are detected only when the affected area is accessed again. If a latent error is detect...
Ningfang Mi, Alma Riska, Evgenia Smirni, Erik Ried...
VLSID
2004
IEEE
117views VLSI» more  VLSID 2004»
14 years 7 months ago
Evaluating the Reliability of Defect-Tolerant Architectures for Nanotechnology with Probabilistic Model Checking
As we move from deep submicron technology to nanotechnology for device manufacture, the need for defect-tolerant architectures is gaining importance. This is because, at the nanos...
Gethin Norman, David Parker, Marta Z. Kwiatkowska,...