49 search results - page 4 / 10 » Remove the memory wall: from performance modeling to archite... |
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
The memory subsystem is a major contributor to the performance, power, and area of complex SoCs used in feature rich multimedia products. Hence, memory architecture of the embedded...
SPAA
1996
ACM
13 years 11 months ago
1996
ACM
Several recent papers have proposed or analyzed optimal algorithms to route all-to-all personalizedcommunication (AAPC) over communication networks such as meshes, hypercubes and ...
ISCA
2006
IEEE
13 years 7 months ago
2006
IEEE
: Tiled architectures, such as RAW, SmartMemories, TRIPS, and WaveScalar, promise to address several issues facing conventional processors, including complexity, wire-delay, and pe...
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
While microprocessor designers turn to multicore architectures to sustain performance expectations, the dramatic increase in parallelism of such architectures will put substantial...
CF
2011
ACM
12 years 7 months ago
2011
ACM
Dynamic Information Flow Tracking (DIFT) is a powerful technique that can protect unmodified binaries from a broad range of vulnerabilities such as buffer overflow and code inj...