74 search results - page 6 / 15 » Reordering Algorithm for Minimizing Test Power in VLSI Circu... |
140
Voted
VLSID
2003
IEEE
16 years 3 months ago
2003
IEEE
Abstract-- In battery driven portable applications, the minimization of energy, average power, peak power, and peak power differential are equally important to improve reliability ...
127
Voted
ISVLSI
2005
IEEE
15 years 8 months ago
2005
IEEE
— Direct tunneling current is the major component of static power dissipation of a CMOS circuit for technology below 65nm, where the gate dielectric (SiO2) is very low. We intuit...
133
Voted
TVLSI
2008
15 years 2 months ago
2008
Abstract--Technology scaling in the nanometer era has increased the transistor's susceptibility to process variations. The effects of such variations are having a huge impact ...
132
Voted
DAC
2000
ACM
16 years 3 months ago
2000
ACM
In this paper we describe an area efficient power minimization scheme "Control Generated ClockingI` that saves significant amounts of power in datapath registers and clock dr...
102
Voted
GLVLSI
2007
IEEE
15 years 9 months ago
2007
IEEE
The path-delay fault simulation of functional tests on complex circuits such as current processor-based systems is a daunting task. The amount of computing power and memory needed...