74 search results - page 6 / 15 » Reordering Algorithm for Minimizing Test Power in VLSI Circu... |
VLSID
2003
IEEE
14 years 7 months ago
2003
IEEE
Abstract-- In battery driven portable applications, the minimization of energy, average power, peak power, and peak power differential are equally important to improve reliability ...
ISVLSI
2005
IEEE
14 years 28 days ago
2005
IEEE
— Direct tunneling current is the major component of static power dissipation of a CMOS circuit for technology below 65nm, where the gate dielectric (SiO2) is very low. We intuit...
TVLSI
2008
13 years 7 months ago
2008
Abstract--Technology scaling in the nanometer era has increased the transistor's susceptibility to process variations. The effects of such variations are having a huge impact ...
DAC
2000
ACM
14 years 8 months ago
2000
ACM
In this paper we describe an area efficient power minimization scheme "Control Generated ClockingI` that saves significant amounts of power in datapath registers and clock dr...
GLVLSI
2007
IEEE
14 years 1 months ago
2007
IEEE
The path-delay fault simulation of functional tests on complex circuits such as current processor-based systems is a daunting task. The amount of computing power and memory needed...