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ISCA
2006
IEEE
130views Hardware» more  ISCA 2006»
13 years 7 months ago
Area-Performance Trade-offs in Tiled Dataflow Architectures
: Tiled architectures, such as RAW, SmartMemories, TRIPS, and WaveScalar, promise to address several issues facing conventional processors, including complexity, wire-delay, and pe...
Steven Swanson, Andrew Putnam, Martha Mercaldi, Ke...
HPCA
2005
IEEE
14 years 1 months ago
Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses
With technology scaling, power dissipation and localized heating in global and semi-global bus wires are becoming increasingly important, and this necessitates the development of ...
Krishnan Sundaresan, Nihar R. Mahapatra
SBACPAD
2006
IEEE
102views Hardware» more  SBACPAD 2006»
14 years 1 months ago
Ultra-Fast CPU Performance Prediction: Extending the Monte Carlo Approach
Performance evaluation of contemporary processors is becoming increasingly difficult due to the lack of proper frameworks. Traditionally, cycle-accurate simulators have been exte...
Ram Srinivasan, Jeanine Cook, Olaf M. Lubeck
ASPLOS
2006
ACM
14 years 1 months ago
Tartan: evaluating spatial computation for whole program execution
Spatial Computing (SC) has been shown to be an energy-efficient model for implementing program kernels. In this paper we explore the feasibility of using SC for more than small k...
Mahim Mishra, Timothy J. Callahan, Tiberiu Chelcea...
ASPLOS
1994
ACM
13 years 11 months ago
Interleaving: A Multithreading Technique Targeting Multiprocessors and Workstations
There is an increasing trend to use commodity microprocessors as the compute engines in large-scale multiprocessors. However, given that the majority of the microprocessors are so...
James Laudon, Anoop Gupta, Mark Horowitz