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» Resilient design in scaled CMOS for energy efficiency
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CODES
2007
IEEE
13 years 11 months ago
Energy efficient co-scheduling in dynamically reconfigurable systems
Energy consumption is a major issue in dynamically reconfigurable systems because of the high power requirements during repeated configurations. Hardware designs employ low power ...
Pao-Ann Hsiung, Pin-Hsien Lu, Chih-Wen Liu
GLVLSI
2007
IEEE
172views VLSI» more  GLVLSI 2007»
14 years 1 months ago
The effect of temperature on cache size tuning for low energy embedded systems
Energy consumption is a major concern in embedded computing systems. Several studies have shown that cache memories account for about 40% or more of the total energy consumed in t...
Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki ...
TPDS
2008
169views more  TPDS 2008»
13 years 7 months ago
Dynamic Resource Management in Energy Constrained Heterogeneous Computing Systems Using Voltage Scaling
An ad hoc grid is a wireless heterogeneous computing environment without a fixed infrastructure. This study considers wireless devices that have different capabilities, have limite...
Jong-Kook Kim, Howard Jay Siegel, Anthony A. Macie...
DAC
2004
ACM
13 years 11 months ago
Enabling energy efficiency in via-patterned gate array devices
In an attempt to enable the cost-effective production of lowand mid-volume application-specific chips, researchers have proposed a number of so-called structured ASIC architecture...
R. Reed Taylor, Herman Schmit
VLSID
2003
IEEE
183views VLSI» more  VLSID 2003»
14 years 8 months ago
Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks
We present an innovative design of an accurate, 2D DCT IDCT processor, which handles scaled and sub-sampled input blocks efficiently. In the IDCT mode, the latency of the processo...
Rohini Krishnan, Om Prakash Gangwal, Jos T. J. van...