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» Resilient design in scaled CMOS for energy efficiency
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ISLPED
2005
ACM
123views Hardware» more  ISLPED 2005»
14 years 1 months ago
Coordinated, distributed, formal energy management of chip multiprocessors
Designers are moving toward chip-multiprocessors (CMPs) to leverage application parallelism for higher performance while keeping design complexity under control. However, to date,...
Philo Juang, Qiang Wu, Li-Shiuan Peh, Margaret Mar...
ASPDAC
2007
ACM
174views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Energy-Efficient Real-Time Task Scheduling in Multiprocessor DVS Systems
Dynamic voltage scaling (DVS) circuits have been widely adopted in many computing systems to provide tradeoff between performance and power consumption. The effective use of energ...
Jian-Jia Chen, Chuan-Yue Yang, Tei-Wei Kuo, Chi-Sh...
JCM
2007
126views more  JCM 2007»
13 years 7 months ago
Design Concepts and First Implementations for 24 GHz Wireless Sensor Nodes
— This paper reviews proposed realization concepts and achievements of wireless sensor nodes and focuses on new developments in the 24 GHz frequency range. The relatively high fr...
Stefan von der Mark, Meik Huber, Georg Boeck
CONEXT
2007
ACM
13 years 11 months ago
Internet routing resilience to failures: analysis and implications
Internet interdomain routing is policy-driven, and thus physical connectivity does not imply reachability. On average, routing on today's Internet works quite well, ensuring ...
Jian Wu, Ying Zhang, Zhuoqing Morley Mao, Kang G. ...
DATE
2006
IEEE
82views Hardware» more  DATE 2006»
14 years 1 months ago
Power-aware compilation for embedded processors with dynamic voltage scaling and adaptive body biasing capabilities
Traditionally, active power has been the primary source of power dissipation in CMOS designs. Although, leakage power is becoming increasingly more important as technology feature...
Po-Kuan Huang, Soheil Ghiasi