133 search results - page 6 / 27 » Resilient design in scaled CMOS for energy efficiency |
ISLPED
2000
ACM
13 years 12 months ago
2000
ACM
Processors in portable electronic devices generally have a computational load which has time-varying performance requirements. Dynamic Voltage Scaling is a method to vary the proc...
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
—A low-power high-SFDR CMOS direct digital frequency synthesizer (DDFS) is presented. Several design techniques, including a cell-based lookup table, a power aware parameters sel...
VLSID
2005
IEEE
14 years 8 months ago
2005
IEEE
Inter-wire coupling is a major source of power consumption and delay faults for on-chip buses implemented in UDSM SoC Systems. Elimination or minimization of such faults is crucia...
ASAP
2006
IEEE
13 years 11 months ago
2006
IEEE
A popular approach to guarantee fault tolerance in safety-critical applications is to run the application on two processors. A checkpoint is inserted at the completion of the prim...
CORR
2010
Springer
13 years 6 months ago
2010
Springer
A critical need in Mobile Wireless Sensor Network (MWSN) is to achieve energy efficiency during routing as the sensor nodes have scarce energy resource. The nodes’ mobility in M...