66 search results - page 7 / 14 » Retargetable compilation for low power |
IAJIT
2010
13 years 8 months ago
2010
: This paper proposes a pipelined, systolic architecture for two- dimensional discrete Fourier transform computation which is highly concurrent. The architecture consists of two, o...
ASPDAC
2004
ACM
14 years 3 months ago
2004
ACM
— For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the instruction memory of embedded processors. In particular, software controlled ...
IJES
2007
13 years 9 months ago
2007
Abstract: Tomorrow’s embedded devices need to run high-resolution multimedia applications which need an enormous computational complexity with a very low energy consumption const...
CASES
2005
ACM
13 years 11 months ago
2005
ACM
Interconnection networks have been deployed as the communication fabric in a wide range of parallel computer systems. With recent technological trends allowing growing quantities ...
TSP
2008
13 years 9 months ago
2008
The focus of this paper is on VLIW instruction scheduling that minimizes the variation of power consumed by the processor during the execution of a target program. We use rough set...