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» Reuse Technique in Hardware Design
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DATE
2005
IEEE
110views Hardware» more  DATE 2005»
14 years 3 months ago
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture
The increasing complexity and the short life cycles of embedded systems are pushing the current system-onchip designs towards a rapid increasing on the number of programmable proc...
Alexandre M. Amory, Marcelo Lubaszewski, Fernando ...
SIPS
2008
IEEE
14 years 4 months ago
Analysis of belief propagation for hardware realization
Belief propagation has become a popular technique for solving computer vision problems, such as stereo estimation and image denoising. However, it requires large memory and bandwi...
Chao-Chung Cheng, Chia-Kai Liang, Yen-Chieh Lai, H...
ICCD
2000
IEEE
50views Hardware» more  ICCD 2000»
14 years 2 months ago
Output Prediction Logic: A High-Performance CMOS Design Technique
Larry McMurchie, Su Kio, Gin Yee, Tyler Thorp, Car...
DAC
1998
ACM
14 years 10 months ago
Power Optimization of Variable Voltage Core-Based Systems
The growing class of portable systems, such as personal computing and communication devices, has resulted in a new set of system design requirements, mainly characterized by domin...
Inki Hong, Darko Kirovski, Gang Qu, Miodrag Potkon...
DSD
2005
IEEE
123views Hardware» more  DSD 2005»
14 years 3 months ago
Hardware-Based Implementation of the Common Approximate Substring Algorithm
An implementation of an algorithm for string matching, commonly used in DNA string analysis, using configurable technology is proposed. The design of the circuit allows for pipeli...
Kenneth B. Kent, Sharon Van Schaick, Jacqueline E....