Sciweavers

2778 search results - page 540 / 556
» Reuse Technique in Hardware Design
Sort
View
CODES
2005
IEEE
14 years 29 days ago
Aggregating processor free time for energy reduction
Even after carefully tuning the memory characteristics to the application properties and the processor speed, during the execution of real applications there are times when the pr...
Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, ...
ISLPED
2004
ACM
123views Hardware» more  ISLPED 2004»
14 years 23 days ago
An efficient voltage scaling algorithm for complex SoCs with few number of voltage modes
Increasing demand for larger high-performance applications requires developing more complex systems with hundreds of processing cores on a single chip. To allow dynamic voltage sc...
Bita Gorjiara, Nader Bagherzadeh, Pai H. Chou
ESAS
2004
Springer
14 years 22 days ago
Public Key Cryptography in Sensor Networks - Revisited
The common perception of public key cryptography is that it is complex, slow and power hungry, and as such not at all suitable for use in ultra-low power environments like wireless...
Gunnar Gaubatz, Jens-Peter Kaps, Berk Sunar
OOPSLA
2004
Springer
14 years 20 days ago
Method-level phase behavior in java workloads
Java workloads are becoming more and more prominent on various computing devices. Understanding the behavior of a Java workload which includes the interaction between the applicat...
Andy Georges, Dries Buytaert, Lieven Eeckhout, Koe...
PLDI
2003
ACM
14 years 17 days ago
Compile-time dynamic voltage scaling settings: opportunities and limits
With power-related concerns becoming dominant aspects of hardware and software design, significant research effort has been devoted towards system power minimization. Among run-t...
Fen Xie, Margaret Martonosi, Sharad Malik