242 search results - page 13 / 49 » Reversible Fault-Tolerant Logic |
ECRTS
2000
IEEE
13 years 11 months ago
2000
IEEE
Internal clock synchronization has been investigated, or employed, for quite a number of years, under the requirement of good upper bounds for the deviation, or accuracy, between ...
VLSID
2006
IEEE
14 years 7 months ago
2006
IEEE
In this paper, a new realization for logic functions, namely Reversible Programmable Logic Array (RPLA), has been proposed. The proposed realization has the advantage of regularit...
SAC
2006
ACM
14 years 20 days ago
2006
ACM
We provide sufficient conditions that formally guarantee that the floating-point computation of a polynomial evaluation is faithful. To this end, we develop a formalization of ï¬...
EUSFLAT
2009
13 years 4 months ago
2009
This paper presents SaM, a split and merge algorithm for frequent item set mining. Its distinguishing qualities are an exceptionally simple algorithm and data structure, which not ...
DATE
2010
IEEE
13 years 11 months ago
2010
IEEE
Abstract—We propose a novel synthesis technique for reversible logic based on ant colony optimization (ACO). In our ACO-based approach, reversible logic synthesis is formulated a...