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CAISE
2005
Springer
14 years 27 days ago
Dynamic Load Balancing of Virtualized Database Services Using Hints and Load Forecasting
Abstract. Future database application systems will be designed as Service Oriented Architectures (SOAs), in contrast to today’s monolithic architectures. The decomposition in man...
Daniel Gmach, Stefan Krompass, Stefan Seltzsam, Ma...
CDES
2006
158views Hardware» more  CDES 2006»
13 years 8 months ago
A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs
In this paper, a double precision IEEE 754 floating-point multiplier with high speed and low power is presented. The bottleneck of any double precision floatingpoint multiplier des...
Himanshu Thapliyal, Vishal Verma, Hamid R. Arabnia
DSD
2010
IEEE
190views Hardware» more  DSD 2010»
13 years 7 months ago
Hardware-Based Speed Up of Face Recognition Towards Real-Time Performance
— Real-time face recognition by computer systems is required in many commercial and security applications because it is the only way to protect privacy and security in the sea of...
I. Sajid, Sotirios G. Ziavras, M. M. Ahmed
BMCBI
2007
111views more  BMCBI 2007»
13 years 7 months ago
Modular co-evolution of metabolic networks
Background: The architecture of biological networks has been reported to exhibit high level of modularity, and to some extent, topological modules of networks overlap with known f...
Jing Zhao, Guohui Ding, Lin Tao, Hong Yu, Zhong-Ha...
DAC
2009
ACM
14 years 8 months ago
Double patterning lithography friendly detailed routing with redundant via consideration
In double patterning lithography (DPL), coloring conflict and stitch minimization are the two main challenges. Post layout decomposition algorithm [1] [2]may not be enough to achi...
Kun Yuan, Katrina Lu, David Z. Pan