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EURODAC
1994
IEEE
145views VHDL» more  EURODAC 1994»
13 years 11 months ago
Testability analysis and improvement from VHDL behavioral specifications
This paper presents a testability improvement method for digital systems described in VHDL behavioral specification. The method is based on testability analysis at registertransfe...
Xinli Gu, Krzysztof Kuchcinski, Zebo Peng
GECCO
2010
Springer
169views Optimization» more  GECCO 2010»
13 years 11 months ago
Robust symbolic regression with affine arithmetic
We use affine arithmetic to improve both the performance and the robustness of genetic programming for symbolic regression. During evolution, we use affine arithmetic to analyze e...
Cassio Pennachin, Moshe Looks, João A. de V...
MOBISYS
2006
ACM
14 years 7 months ago
LIGER: implementing efficient hybrid security mechanisms for heterogeneous sensor networks
The majority of security schemes available for sensor networks assume deployment in areas without access to a wired infrastructure. More specifically, nodes in these networks are ...
Patrick Traynor, Raju Kumar, Hussain Bin Saad, Guo...
VLSID
2001
IEEE
164views VLSI» more  VLSID 2001»
14 years 8 months ago
An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...
Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das
DATE
2009
IEEE
120views Hardware» more  DATE 2009»
14 years 2 months ago
Overcoming limitations of the SystemC data introspection
—Today verification, testing and debugging of SystemC models can be applied at an early stage in the design process. To support these techniques gaining required information of ...
Christian Genz, Rolf Drechsler