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AGILEDC
2003
IEEE
15 years 10 months ago
PARFAIT: Towards a Framework-based Agile Reengineering Process
The paper presents a sketch of a framework-based agile reengineering process, named PARFAIT1 , whose objective is to provide the users with evolved versions of legacy systems, as ...
Maria Istela Cagnin, José Carlos Maldonado,...
ANSS
2003
IEEE
15 years 10 months ago
An ns-based Bluetooth Topology Construction Simulation Environment
Bluetooth is an emerging technology in wireless applications, and many related issues are yet to be explored both in academia and industry. Because of the complexity and the dynam...
Chia-Jui Hsu, Yuh-Jzer Joung
ASAP
2003
IEEE
169views Hardware» more  ASAP 2003»
15 years 10 months ago
Combined Multiplication and Sum-of-Squares Units
Multiplication and squaring are important operations in digital signal processing and multimedia applications. This paper presents designs for units that implement either multipli...
Michael J. Schulte, Louis Marquette, Shankar Krith...
ATS
2003
IEEE
131views Hardware» more  ATS 2003»
15 years 10 months ago
Software-Based Delay Fault Testing of Processor Cores
Software-based self-testing is a promising approach for the testing of processor cores which are embedded inside a System-on-a-Chip (SoC), as it can apply test vectors in function...
Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hi...
CODES
2003
IEEE
15 years 10 months ago
A codesigned on-chip logic minimizer
Boolean logic minimization is traditionally used in logic synthesis tools running on powerful desktop computers. However, logic minimization has recently been proposed for dynamic...
Roman L. Lysecky, Frank Vahid
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