768 search results - page 140 / 154 » Robustness of Sequential Circuits |
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
This paper proposes an innovative methodology to perform and validate a Failure Mode and Effects Analysis (FMEA) at System-on-Chip (SoC) level. This is done in compliance with the...
DDECS
2007
IEEE
14 years 2 months ago
2007
IEEE
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
ESCIENCE
2007
IEEE
14 years 2 months ago
2007
IEEE
The electronics design industry is facing major challenges as transistors continue to decrease in size. The next generation of devices will be so small that the position of indivi...
ICRA
2007
IEEE
14 years 2 months ago
2007
IEEE
— This article presents a control architecture for controlling the locomotion of an amphibious snake/lamprey robot capable of swimming and serpentine locomotion. The control arch...
VTS
2007
IEEE
14 years 2 months ago
2007
IEEE
: Conventionally, path delay tests are derived in a delay-independent manner, which causes most faults to be robustly untestable. Many non-robust tests are found but, in practice, ...