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search results - page 21 / 154
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Robustness of Sequential Circuits
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GLVLSI
1998
IEEE
106
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VLSI
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GLVLSI 1998
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Test Compaction for Synchronous Sequential Circuits by Test Sequence Recycling
14 years 1 months ago
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www.cs.york.ac.uk
Irith Pomeranz, Sudhakar M. Reddy
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33
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VTS
1998
IEEE
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Hardware
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VTS 1998
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On the Identification of Optimal Cellular Automata for Built-In Self-Test of Sequential Circuits
14 years 1 months ago
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www.cad.polito.it
This paper presents a BIST architecture for Finite State Machines that exploits Cellular Automata (CA) as pattern generators and signature analyzers. The main advantage of the pro...
Fulvio Corno, Nicola Gaudenzi, Paolo Prinetto, Mat...
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DATE
1997
IEEE
76
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Hardware
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DATE 1997
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New static compaction techniques of test sequences for sequential circuits
14 years 1 months ago
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www.cecs.uci.edu
Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo,...
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DAC
1996
ACM
84
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Computer Architecture
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DAC 1996
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Optimal Clock Period FPGA Technology Mapping for Sequential Circuits
14 years 1 months ago
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www.eecs.berkeley.edu
Peichen Pan, C. L. Liu
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EURODAC
1994
IEEE
115
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VHDL
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EURODAC 1994
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Control Path Oriented Verification of Sequential Generic Circuits with Control and Data Path
14 years 1 months ago
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es.cs.uni-kl.de
Klaus Schneider, Thomas Kropf, Ramayya Kumar
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