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DATE
2007
IEEE
85views Hardware» more  DATE 2007»
14 years 3 months ago
QuteSAT: a robust circuit-based SAT solver for complex circuit structure
We propose a robust circuit-based Boolean Satisfiability (SAT) solver, QuteSAT, that can be applied to complex circuit netlist structure. Several novel techniques are proposed in ...
Chi-An Wu, Ting-Hao Lin, Chih-Chun Lee, Chung-Yang...
ICCAD
1998
IEEE
95views Hardware» more  ICCAD 1998»
14 years 1 months ago
Efficient analog circuit synthesis with simultaneous yield and robustness optimization
This paper presents an efficient statistical design methodology that allows simultaneous sizing for performance and optimization for yield and robustness of analog circuits. The s...
Geert Debyser, Georges G. E. Gielen
ICCAD
2002
IEEE
126views Hardware» more  ICCAD 2002»
14 years 1 months ago
Robust and passive model order reduction for circuits containing susceptance elements
Numerous approaches have been proposed to address the overwhelming modeling problems that result from the emergence of magnetic coupling as a dominant performance factor for ICs a...
Hui Zheng, Lawrence T. Pileggi
BIBE
2008
IEEE
14 years 3 months ago
Robust parameter identification for biological circuit calibration
Abstract-The aim of this work is to compare some deterministic optimization algorithms and evolutionary algorithms on parameter estimation in a biological circuit design problem: t...
Giuseppe Nicosia, Eva Sciacca
INFSOF
2006
103views more  INFSOF 2006»
13 years 8 months ago
Improving test quality using robust unique input/output circuit sequences (UIOCs)
In finite state machine (FSM) based testing, the problem of fault masking in the unique input/output (UIO) sequence may degrade the test performance of the UIO based methods. This...
Qiang Guo, Robert M. Hierons, Mark Harman, Karnig ...