768 search results - page 39 / 154 » Robustness of Sequential Circuits |
VTS
2006
IEEE
14 years 2 months ago
2006
IEEE
Abstract: An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU...
ISMVL
2000
IEEE
14 years 1 months ago
2000
IEEE
A sequential realization of multiple-output logic functions is presented. A conventional sequential realization is based on SBDDs (Shared reduced ordered Binary Decision Diagrams)...
ICCAD
2007
IEEE
14 years 5 months ago
2007
IEEE
An algorithm for technology mapping of combinational and sequential logic networks is proposed and applied to mapping into K-input lookup-tables (K-LUTs). The new algorithm avoids...
ICCAD
2001
IEEE
14 years 5 months ago
2001
IEEE
SPFDs are a mechanism to express flexibility in Boolean networks. Introduced by Yamashita et al. in the context of FPGA synthesis [4], they were extended later to general combina...
FMCAD
2004
Springer
14 years 2 months ago
2004
Springer
Late changes in silicon design (ECO) is a common although undesired practice. The need for ECO exists even in high-level design flows since bugs may occur in the specifications, ...