Design Optimization for Robustness to Single Event Upsets

Abstract: An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustness of a logic gate is developed. This model is integrated with area and performance constraints into an optimization framework based on geometric programming for design space exploration. Simulation results demonstrate the design tradeoffs that can be achieved with this approach.

• Type: Conference
• Year: 2006
• Where: VTS
• Authors: Quming Zhou, Mihir R. Choudhury, Kartik Mohanram
• Keywords: Combinational Circuits, SEU Robustness, Single-event Upsets, VTS 2006