768 search results - page 45 / 154 » Robustness of Sequential Circuits |
JUCS
2007
13 years 8 months ago
2007
: This article presents an architecture that encrypts data with the AES algorithm. This architecture can be implemented on the Xilinx Virtex II FPGA family, by applying pipelining ...
BIRTHDAY
2003
Springer
14 years 2 months ago
2003
Springer
Abstract. Digital numbers D are the world’s most popular data representation: nearly all texts, sounds and images are coded somewhere in time and space by binary sequences. The m...
DAC
2006
ACM
14 years 2 months ago
2006
ACM
This paper investigates methods for clock skew minimization using buffer and wire sizing. First, a technique that significantly improves solution quality and stability of sequent...
ASPDAC
2006
ACM
14 years 2 months ago
2006
ACM
Commonly used pattern sources in simulation-based verification include random, guided random, or design verification patterns. Although these patterns may help bring the design ...
ICCAD
2006
IEEE
14 years 5 months ago
2006
IEEE
An approach to robust system level mixed signal design is presented based on analog platforms. The bottom-up characterization phase of platform components provides accurate perfor...