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» Robustness of Sequential Circuits
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ICCAD
1997
IEEE
144views Hardware» more  ICCAD 1997»
14 years 1 months ago
Partial scan delay fault testing of asynchronous circuits
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...
Michael Kishinevsky, Alex Kondratyev, Luciano Lava...
TEC
2002
119views more  TEC 2002»
13 years 8 months ago
Graph-based evolutionary design of arithmetic circuits
Abstract--In this paper, we present an efficient graph-based evolutionary optimization technique called evolutionary graph generation (EGG) and the proposed approach is applied to ...
Dingjun Chen, Takafumi Aoki, Naofumi Homma, Toshik...
ICCAD
1995
IEEE
94views Hardware» more  ICCAD 1995»
14 years 11 days ago
Test register insertion with minimum hardware cost
Implementing a built-in self-test by a "test per clock" scheme offers advantages concerning fault coverage, detection of delay faults, and test application time. Such a ...
Albrecht P. Stroele, Hans-Joachim Wunderlich
FMSD
2000
80views more  FMSD 2000»
13 years 8 months ago
Delay-Insensitivity and Semi-Modularity
The study of asynchronous circuit behaviors in the presence of component and wire delays has received a great deal of attention. In this paper, we consider asynchronous circuits wh...
Janusz A. Brzozowski, Hao Zhang 0002
ISQED
2006
IEEE
85views Hardware» more  ISQED 2006»
14 years 2 months ago
Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold Times
— A methodology is proposed for interdependent setup time and hold time characterization of sequential circuits. Integrating the methodology into an industrial sign-off static ti...
Emre Salman, Eby G. Friedman, Ali Dasdan, Feroze T...