116 search results - page 12 / 24 » Route Packets, Not Wires: On-Chip Interconnection Networks |
ANCS
2006
ACM
14 years 2 months ago
2006
ACM
Clos networks are an important class of switching networks due to their modular structure and much lower cost compared with crossbars. For routing I/O permutations of Clos network...
NOCS
2010
IEEE
13 years 7 months ago
2010
IEEE
A new asynchronous interconnection network is introduced for globally-asynchronous locally-synchronous (GALS) chip multiprocessors. The network eliminates the need for global cloc...
ICPADS
2005
IEEE
14 years 2 months ago
2005
IEEE
We show that universal routing can be achieved with low overhead in distributed networks. The validity of our results rests on a new network called the fat-stack. We show that fro...
3DIC
2009
IEEE
13 years 12 months ago
2009
IEEE
Abstract— Networks-on-chip (NoC) is emerging as a key onchip communication architecture for multiprocessor systemson-chip (MPSoC). In traditional electronic NoCs, high bandwidth ...
ANCS
2005
ACM
14 years 2 months ago
2005
ACM
This paper investigates the suitability of emerging tiled-architectures, equipped with low-latency on-chip networks, for high-performance network routing. In this paper, we presen...