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EURODAC
1994
IEEE
120views VHDL» more  EURODAC 1994»
15 years 8 months ago
Planar-DME: improved planar zero-skew clock routing with minimum pathlength delay
Clock routing has become a critical issue in the layout design of high-performance systems. We show that the two passes bottom-up and top-down of the DME algorithm 2, 3, 4, 8 can ...
Chung-Wen Albert Tsao, Andrew B. Kahng
JNCA
2011
281views more  JNCA 2011»
14 years 7 months ago
A link stability-based multicast routing protocol for wireless mobile ad hoc networks
  Recently, several studies have been conducted to design mobility‐based multicast routing protocols for    wireless mobile ad hoc networks (MANET). These ...
Javad Akbari Torkestani, Mohammad Reza Meybodi
DATE
2007
IEEE
109views Hardware» more  DATE 2007»
15 years 10 months ago
System level clock tree synthesis for power optimization
The clock tree is the interconnect net on Systems-on-Chip (SoCs) with the heaviest load and consumes up to 40% of the overall power budget. Substantial savings of the overall powe...
Saif Ali Butt, Stefan Schmermbeck, Jurij Rosenthal...
DAC
2005
ACM
16 years 5 months ago
Multilevel full-chip routing for the X-based architecture
As technology advances into the nanometer territory, the interconnect delay has become a first-order effect on chip performance. To handle this effect, the X-architecture has been...
Tsung-Yi Ho, Chen-Feng Chang, Yao-Wen Chang, Sao-J...
SASP
2009
IEEE
291views Hardware» more  SASP 2009»
15 years 10 months ago
FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs
— As growing power dissipation and thermal effects disrupted the rising clock frequency trend and threatened to annul Moore’s law, the computing industry has switched its route...
Alexandros Papakonstantinou, Karthik Gururaj, John...