78 search results - page 9 / 16 » Router designs for elastic buffer on-chip networks |
ASYNC
2005
IEEE
14 years 1 months ago
2005
IEEE
Networks on Chip that can guarantee Quality of Service (QNoC) are based on special routers that can support multiple service levels. GALS SoCs call for asynchronous NoC implementa...
INFOCOM
1998
IEEE
13 years 11 months ago
1998
IEEE
Memory bandwidth is frequently a limiting factor in the design of high-speed switches and routers. In this paper, we introduce a buffering scheme called ping-pong buffering, that ...
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
As chip multiprocessors (CMPs) become the only viable way to scale up and utilize the abundant transistors made available in current microprocessors, the design of on-chip network...
CNSR
2010
IEEE
13 years 10 months ago
2010
IEEE
— Buffered crossbar (CICQ) switches have shown a high potential in scaling Internet routers capacity. However, they require expensive on-chip buffers whose cost grows quadratical...
VLSID
2004
IEEE
14 years 7 months ago
2004
IEEE
In this paper, we describe NoCGEN, a Network On Chip (NoC) generator, which is used to create a simulatable and synthesizable NoC description. NoCGEN uses a set of modularised rou...