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ICCAD
1997
IEEE
90views Hardware» more  ICCAD 1997»
15 years 7 months ago
A hierarchical decomposition methodology for multistage clock circuits
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar
126
Voted
ICCAD
1996
IEEE
122views Hardware» more  ICCAD 1996»
15 years 7 months ago
Analytical delay models for VLSI interconnects under ramp input
Elmore delay has been widely used as an analytical estimate of interconnect delays in the performance-driven synthesis and layout of VLSI routing topologies. However,for typical R...
Andrew B. Kahng, Kei Masuko, Sudhakar Muddu
SIGOPSE
1992
ACM
15 years 7 months ago
Names should mean what, not where
Abstract-- This paper describes the design and implementation1 of IRIS: an intentional resource indicator service. IRIS springs from the concept that end-users should not be bogged...
James O'Toole, David K. Gifford
DSD
2006
IEEE
131views Hardware» more  DSD 2006»
15 years 7 months ago
Designing Efficient Irregular Networks for Heterogeneous Systems-on-Chip
Abstract-- Networks-on-Chip will serve as the central integration platform in future complex SoC designs, composed of a large number of heterogeneous processing resources. Most res...
Christian Neeb, Norbert Wehn
140
Voted
CIKM
2006
Springer
15 years 5 months ago
Processing relaxed skylines in PDMS using distributed data summaries
Peer Data Management Systems (PDMS) are a natural extension of heterogeneous database systems. One of the main tasks in such systems is efficient query processing. Insisting on co...
Katja Hose, Christian Lemke, Kai-Uwe Sattler