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ASPDAC
2010
ACM
135views Hardware» more  ASPDAC 2010»
13 years 7 months ago
Statistical timing verification for transparently latched circuits through structural graph traversal
Level-sensitive transparent latches are widely used in high-performance sequential circuit designs. Under process variations, the timing of a transparently latched circuit will ada...
Xingliang Yuan, Jia Wang
DALT
2009
Springer
14 years 1 months ago
Social Commitments in Time: Satisfied or Compensated
Abstract. We define a framework based on computational logic technology and on a reactive axiomatization of the Event Calculus to formalize the evolution of commitments in time. We...
Paolo Torroni, Federico Chesani, Paola Mello, Marc...
TSE
2008
236views more  TSE 2008»
13 years 9 months ago
Provable Protection against Web Application Vulnerabilities Related to Session Data Dependencies
Web applications are widely adopted and their correct functioning is mission critical for many businesses. At the same time, Web applications tend to be error prone and implementat...
Lieven Desmet, Pierre Verbaeten, Wouter Joosen, Fr...
WICSA
2004
13 years 11 months ago
Style-Based Refinement of Dynamic Software Architectures
In this paper, we address the correct refinement of abstract architectural models into more platformspecific representations. We consider the challenging case of dynamic architect...
Luciano Baresi, Reiko Heckel, Sebastian Thöne...
ASE
2010
129views more  ASE 2010»
13 years 10 months ago
Efficient monitoring of parametric context-free patterns
Recent developments in runtime verification and monitoring show that parametric regular and temporal logic specifications can be efficiently monitored against large programs. Howev...
Patrick O'Neil Meredith, Dongyun Jin, Feng Chen, G...