Statistical timing verification for transparently latched circuits through structural graph traversal

Level-sensitive transparent latches are widely used in high-performance sequential circuit designs. Under process variations, the timing of a transparently latched circuit will adapt random delays at runtime due to time borrowing. The central problem to determine the timing yield is to compute the probability of the presence of a positive cycle in the latest latch timing graph. Existing algorithms are either optimistic since cycles are omitted or require iterations that cannot be polynomially bounded. In this paper, we present the first algorithm to compute such probability based on block-based statistical timing analysis that, first, covers all cycles through a structural graph traversal, and second, terminates within a polynomial number of statistical "sum" and "max" operations. Experimental results confirm that the proposed approach is effective and efficient.

• Type: Journal
• Year: 2010
• Where: ASPDAC
• Authors: Xingliang Yuan, Jia Wang
• Keywords: ASPDAC 2010, Block-based Statistical Timing, Hardware, Level-sensitive Transparent Latches, Structural Graph Traversal